Method for controlling the addressing of an AC plasma display panel

ABSTRACT

A control process for addressing an AC plasma panel. The panel includes line electrodes crossed with column electrodes where the intersections of these electrodes define cells. Sustain signals are applied to all of the line electrodes by way of at least one control circuit. The cells are addressed by superimposing supplementary voltage porches onto the sustain signals and then subsequently superimposing addresses pulses onto the supplementary porches. This method makes it possible to reduce the amplitude of the addressing pulses, thus resulting in a lesser demand on the control circuits resulting in a reduction of capacitive consumption.

BACKGROUND OF THE INVENTION

1. Fields of the Invention

The present invention relates to a control process for addressing an ACtype plasma panel. For components used for addressing operations, itsimplementation makes it possible in particular to reduce the performancerequired from these components and hence to reduce their cost. Theinvention also relates to a plasma panel operating according to thisprocess.

2. Discussion of the Background

Plasma panels or plasma screens, abbreviated to “PAPs” in the subsequentdescription, are flat display screens which use the emission ofradiation in the visible or ultra-violet spectrum from a discharge ingases.

PAPs consist mainly of two large families, PAPs of the so-called DC typeand PAPs of the so-called AC type. PAPs of the AC type, owing to theirparticular structure, benefit operationally from an effect referred toas the “memory effect” which renders them especially suitable inconstructing large screens with a large number of elementary cells, bothfor professional applications and those aimed at the general public,such as for example high-definition colour television.

There are various types of AC PAP:

for example PAPs which use only two electrodes crossed to define a celland to carry out its addressing and its activation, as described inFrench Patent 2 417 848:

or else AC PAPs of the so-called “coplanar sustain” type, known inparticular through the European Patent document EP-A-0135 382, and inwhich each cell is defined at the crossing of a pair of so-calledsustain electrodes with one or more other electrodes used moreparticularly for addressing the cells.

With AC PAPs, the addressing functions and those aimed at producing thelight energy are separated: the production of light results from the“parallel” application to all the cells of a square-wave strobe signalreferred to as the “sustain signal”.

By contrast, the addressing of the cells demands that it be possible tocontrol each line and each column of cells in an individualized manner.The electronic means serving to carry out these individualized controlsare relatively complex and expensive, this being all the more penalizingas the market for PAPs moves towards ever larger panels.

The operation of an AC PAP is explained further hereafter with referenceto FIG. 1. To simplify the explanations, the diagram shown in FIG. 1 isthat of a PAP with two electrodes crossed to define a cell.

The PAP comprises a screen 1 formed with the aid of a network ofelectrodes Y1 to Y6 referred to as “line electrodes”, which is crossedwith a second network of electrodes X1 to X6 referred to as columnelectrodes. To each intersection of line and column electrodes therecorresponds a cell C1 to C36. These cells are thus arranged along linesL1 to L6 and columns CL1 to CL6. In the example of FIG. 1, only 6electrodes of each type are represented, but a PAP can include 1000 ormore line electrodes and as many column electrodes, defining 1 millionor more cells.

Each line electrode Y1 to Y6 is linked to a line output stage SY1 to SY6of a line management device 2, and each column electrode X1 to X6 islinked to a column output stage SX1 to SX6 of a column management device3. The operation of these two management devices 2, 3 is controlled byan image management device 4.

The line management device 2 comprises:

at least one circuit referred to as a sustain amplifier A1, producingsignals referred to as “sustain signals” SE serving in activating thecells C1 to C36; given the sizeable power under which the SE signals maypossibly have to be delivered, they may be supplied with the aid of afirst and of a second amplifier A1, A2 as in the example shown;

it also includes in the non-limiting example represented, a first and asecond line control circuit 6, 7 (which correspond to the circuitsreferred to as “line drivers” by experts in the field). In thesimplified representation shown in FIG. 1 of the first and of the secondline control circuit 6, 7, these latter respectively each comprise threeswitching stages M1 to M3 and M4 to M6 each linked to the input of aline output stage SY1 to SY3 and SY4 to SY6, in such a way that thefirst circuit 6 controls the first three line electrodes Y1 to Y3 andthat the second circuit 7 controls the following three electrodes Y4 toY6.

Each line control circuit 6, 7 is linked to one of the amplifiers A1,A2, from which it receives the sustain signals SE, and its function isin particular: on the one hand, to forward these signals SE in such away that they are applied simultaneously to all the line electrodes Y1to Y6 which it controls; its function is on the other hand, for theelectrode or electrodes selected for an addressing operation, tosuperimpose either a so-called write pulse IS or a so-called erase pulseIE onto the sustain signals SE, depending on the type of addressing tobe carried out.

The column management device 3 has in particular the function ofapplying, to the column electrodes X1 to X6, a reference potential, withrespect to which so-called masking pulses IM are applied to some ofthese electrodes during addressing operations. To this end, it employs acolumn control circuit 8, similar for example to the line controlcircuits 6, 7, and comprising in the example, 6 switching stages M7 toM12 each linked to a column output stage SX1 to SX6, and which areresponsible for formulating and switching the masking pulses.

In a PAP, each cell includes a gas-filled space. By applying asufficient voltage referred to as the “turn-on voltage” VA between thetwo electrodes which define a given cell, an electric discharge iscaused in the gas, giving rise to the emission of light by this cell. Inan AC PAP, the electrodes are covered with a dielectric material.Accordingly, with each discharge into the gas, electric chargesaccumulate on the dielectric near the electrodes which define a cellwithin which the discharge occurs. These electric charges persist afterthe discharge and constitute an electric field referred to as the“internal memory field” specific to each cell, and make it possible, inrespect of the cell which possesses it, to cause a discharge with theapplication of a voltage below the turn-on voltage. This effectconstitutes the “memory effect” already mentioned. The cells whichposseses such charges are said to be in the “written” or “on” state. Toproduce a discharge, the other cells demand a voltage equal to theturn-on voltage, they are said to be in the “erased” or “off” state.

The effect of applying the sustain signals SE is to activate the cellsC1 to C36 which are in the “written” state, that is to say to causedischarges in these cells, without modifying their state or the state ofthe cells which are in the “erased” state. The cells are set to the“written” state or the “erased” state depending on an image to bedisplayed, by addressing operations which are often carried out line byline, that is to say for all the cells C1 to C36 belonging to the sameline L1 to L6 (or stated otherwise, for all the cells defined along thesame line electrode Y1 to Y6), and then subsequently for all the cellsof another line.

FIG. 2a represents sustain signals SE of a common type, which areintended to be applied to all the line electrodes Y1 to Y6. They consistof negative voltage strobes 9 and positive voltage strobes 10established on either side of a reference potential V0 (which is oftenthe potential of earth), and which follow one another with oppositepolarities. They vary between a negative potential V1 where they exhibita so-called negative porch p−, and a positive potential V2 where theyexhibit a so-called positive porch p+. These negative and positivepotentials V1, V2 have for example a value of 150 volts, which is addedto the voltage produced by the internal memory field, so as to reachsubstantially the turn-on voltage value VA. According to a common form,the voltage transition which follows the end of a strobe 9; 10 can leaddirectly to the start of the following strobe, or else as in the exampleshown: on the one hand the negative strobes 9 are separated from thepositive strobe 10 which follows by a wide intermediate porch 5, formedat the level of the reference potential V0 and intended to serve as basefor an addressing pulse; and on the other hand, each positive strobe 10is separated from the negative strobe which follows by a narrowintermediate porch 11, formed on the reference potential V0.

The reference potential V0 is applied to the column electrodes X1 to X6in such a way that the application of each of the positive and negativestrobes of the sustain signals SE to the line electrodes Y to Y6develops at the terminals of the cells, alternating voltages of oppositesigns, which give rise to so-called sustain discharges in all the cellswhich are in the “written” state.

FIG. 2b represents the phase relation between the sustain discharges Idin the cells C1 to C36, and the establishing of the strobes 9, 10. Itmay be seen that these discharges occur at instants td arising slightlyafter each start of the negative and positive porches p−, p+; in factthese discharges arise a few hundred nanoseconds after the establishmentof these porches.

The strobes 9, 10 of the sustain signal SE follow one another with aperiod P1, P2, P3, P4 (commonly of the order of 20 microseconds), duringwhich the addressing of all the cells defined by a elected lineelectrode (or by several in certain cases) is performed. The addressingoperations are executed by the line and column control circuits 6, 7,which deliver specific signals for this purpose. The addressingconsists, for the line control circuit 6, 7 and with the aid inparticular of that of the switching stages M1 to M6 corresponding to theselected line electrode, in superimposing an erase pulse IE followed bya write pulse IS onto the sustain signal SE applied to this electrode.

FIGS. 2c, 2 d and 2 e respectively illustrate addressing operationsperformed on the cells of the line electrodes Y1, Y2 and Y3, whichelectrodes are controlled by the first line control circuit 6.

Assuming that the addressing of the line electrode Y1 is performedduring a period P1 starting at an instant t0: the function of the signalapplied solely to this electrode is to set all the cells of thiselectrode to the “erased” state. For this purpose, in the addressingform shown by way of example, a so-called erase addressing pulse IE, ofpositive polarity, is superimposed at an instant t1 on the wideintermediate porch 5 (that is to say the voltage corresponding to theamplitude of the pulse is added algebraically to the voltage onto whichit is superimposed and hence which serves as base therefor) This erasepulse IE can exhibit a relatively slow rise time Tm, and its amplitudeV4 is such that its summit reaches a value V3 referred to as the “erasevoltage”, slightly below for example the voltage V2 of the positivestrobes 10. Such a signal, applied to the line electrode Y1 while thereference potential V0 is applied to all the column electrodes, causes astart of discharge in the cells which are in the “written” state, andits effect is to absorb the accumulated electric charges and henceeliminate the internal memory fields near all the cells.

Erasure can also be accomplished with the aid of an erase pulse IE′(represented dashed) superimposed t the instant t0 during theestablishing of the negative strobe 9, and the shape of which makes itpossible to confer a long time on this establishing time withoutmodifying its amplitude. It should be noted that this addressing isaccomplished under the action of the first switching stage M1 so as tobe applied solely to the first line electrode Y1.

All the cells of the selected electrode Y1 having been erased, the nextphase consists in setting to the “written” state only the selected cellor cells. To this end, a write pulse IS is superimposed on the sustainsignal SE at an instant t2, on the positive porch p+. The pulse IS hasan amplitude V5 such that with this superposition, the resulting voltageV2+V5 reaches a so-called write voltage value which is comparable withthe turn-on voltage VA. If at this moment the potential delivered by allthe column output stages SX1 to SX6, that is to say the potentialapplied to all the column electrodes X1 to X6, is that of the referencepotential V0, the potential difference at the terminals of the cells C1to C6 formed with the line electrode Y1 possesses the value of theturn-on voltage VA: accordingly, discharges occur in all the cells whichconsequently benefit from an internal memory field and are therefore inthe “written” state.

To effect the selection of the cells, the column electrode managementdevice 3 produces, with each write pulse IS, a “masking” sequence whichconsists in applying to those of the column electrodes X1 to X6 whichdefine a cell having to remain in the “erased” state, a masking pulse IMin phase with the write pulse IS and the function of which is to preventthe potential difference at the terminals of these cells from reachingthe turn-on value VA, and thus to disable the action of the write pulseIS.

FIG. 2f represents a masking pulse IM delivered on the second columnelectrode X2, at the instant t2, that is to say in phase with the writepulse IS applied to the first line electrode Y1. The masking pulse IM ispositive, and its presence at this instant means that, at the end of thecycle for addressing the first line electrode Y1, the cell C2 retains an“erased” state.

FIG. 2d illustrates the addressing performed on the second lineelectrode Y2 (with the aid of the second switching stage M2), during asecond period P2 which follows the first period P1. As in the previouscase, the addressing starts with an erasing of all the cells (C7 to C12in the present case) with the aid of an erase pulse IE, superimposed ona wide intermediate porch 5 at an instant t3, this being solely for thesecond line electrode Y2. Next, at an instant t4, a write pulse IS issuperimposed on the positive porch 10 and causes all those cells of thisline for which no masking pulse IM is applied to the correspondingcolumn electrode X1 to X6 to be set to the “written” state. It should benoted that no masking pulse (FIG. 2f) being applied to the second columnelectrode X2 at the instant t4, the cell C8 is set to the “written”state.

FIG. 2e shows the addressings performed on the third line electrode Y3(with the aid of the third switching stage M3), during a third period P3which follows the second P2. At an instant t5, an erase pulse IE issuperimposed on the wide intermediate porch p1. Next, at an instant t6,a write pulse IS is superimposed on the positive porch p+. Theaddressing (not represented) on the line electrodes Y4, Y5, Y6 is thenperformed in the same way, beginning with that of the electrode Y4 whichis performed during the period P4.

The addressing operations described above are of two types: theaddressing which consists in setting all the cells of the same lineelectrode to the same “erased” state without distinction, and of the“semi-selective addressing” type, and that which consists in settingselected cells to the “written” state and of the “selective addressing”type. However, semi-selective and selective addressings can also consistin setting all the cells of the same line to the “written” state for“semi-selective”, and to the “erased” state certain selected cells, asfar as “selective” is concerned. These explanations regarding theoperation of an AC PAP highlight the importance, the large number andthe complexity of the functions fulfilled by a line or column controlcircuit 6, 7 or 8. To cater for all these functions, these controlcircuits are themselves complex electronic components. The higher theperformance demanded of these components, the more sophisticated andexpensive are the technologies employed in their manufacture.

Among the technical characteristics which these control circuits mustexhibit, those which relate to their capacity to deliver high voltagepulses are especially expensive to achieve. This is yet more pronouncedas regards their ability to deliver, simultaneously on their variousoutputs, signals exhibiting large voltage differences, as is the case inthe addressing operations, both in respect of the line control circuits6, 7 which deliver addressing pulses IE, IS, and in respect of thecolumn control circuit delivering masking pulses IM.

It should be observed that the line control circuits 6, 7 must exhibittechnical characteristics of much greater performance in order todeliver the addressing pulses IS, IE than to deliver the sustain signalsSE. This is because the latter are applied continuously to all theelectrodes Y1 to Y6, they need not be selected or switched, they areformulated by the amplifiers A1, A2 and merely pass through theswitching stages M1 to M6. The addressing pulses on the other hand usevarious complex electronic circuits so as to be constructed, selected,switched and superimposed on the sustain signals with the appropriatesynchronism and appropriate rate, and with sufficient power to possiblygive rise to discharges in a large number of cells simultaneously.

The importance of the problem raised by the cost of these controlcircuits is tending to increase further, on account in particular of theever wider applications of PAPs to the displaying of large-size colourimages, since the production of colours requires gas mixtures havinghigher turn-on (ignition) voltages VA.

SUMMARY OF THE INVENTION

One of the aims of the present invention is to allow the use, within ACPAPs, of line control and/or column control circuits exhibiting thelower cost.

Another purpose of the invention is to reduce the so-called capacitiveconsumption of AC PAPs. The capacitances exhibited by the variouselements, such as for example the tracks which constitute theelectrodes, the various connections, and the self-capacitances of theelectronic circuits, form a relatively sizeable overall capacitancewhich consumes AC currents. The capacitive power PC dissipated by anaddressing pulse is expressed through the following relation:

PC=C·Vi²·F; where C is the capacitance seen by the pulse, Vi is thevalue of the voltage of the addressing pulse, F is the addressingfrequency. This relation shows in particular that this capacitive powervaries with the square of the amplitude of the pulse.

To achieve the aforementioned purposes, the invention proposes that theselective and/or semi-selective addressings be done in a manner whichmakes it possible to reduce the amplitude of the addressing pulsesdistributed by the control circuits 6, 7, 8.

The invention relates to a control process for addressing an AC plasmapanel comprising at least one network of so-called “line” electrodes,crossed with at least one network of so-called column electrodes, cellsbeing formed at the intersections of the line and column electrodes, thesaid process consisting in applying to all the line electrodes sustainsignals formed of a succession of strobes having a given period andestablished with respect to a reference potential applied to the columnelectrodes, each period being able to constitute an addressing cyclecomprising at least one addressing of the semi-selective type and atleast one addressing of the selective type, each type of addressingconsisting in applying to at least one selected line electrode aso-called addressing pulse whose voltage is added to a so-called linevoltage already present on this electrode, with a view to applying tothe terminals of cells formed by this selected electrode a so-calledaddressing voltage of given value corresponding to the addressing to beperformed, the process being characterized in that for at least one ofthe two types of addressing, the addressing pulse has an amplitude belowthat which is appropriate for obtaining the required addressing voltage,and in that to obtain the said addressing voltage, it furthermoreconsists either in modifying the reference potential applied to thecolumn electrodes, or in modifying the line voltage already present onthe selected line electrode when the addressing pulse is applied, oralternatively in modifying this latter line voltage as well as thereference potential applied to the column electrodes.

The process according to the invention consists in superimposing atleast one voltage porch referred to as the supplementary porch on thesustain signals during a period of these latter, in such a way as toconstitute a voltage base referred to as the addressing base onto whichis superimposed at least one addressing pulse.

The signals being formed of negative and positive strobes, the processaccording to the invention consists in forming a write addressingvoltage base with a strobe, and of superimposing an addressing pulseconsisting of a so-called write pulse onto this addressing base.

The process consists in establishing between two consecutive strobes anintermediate porch having a voltage below the voltage of the strobes,and in adding a supplementary porch to the said intermediate porch so asto constitute an erase addressing base, then in superimposing anaddressing pulse consisting of an erase pulse onto this erasure base.

The intermediate porch is at the same voltage as the referencepotential.

The supplementary porches added onto strobes are superimposed on theselatter after an instant at which a so-called sustain discharge occurs.

The supplementary porches formed on strobes are deleted substantially atthe end of these strobes.

The supplementary porches formed on strobes encompass the entirety ofthe pulse or pulses for addressing a selected line electrode.

The supplementary porches serving to constitute an erasure base have anamplitude equal to or greater than the difference between a so-callederasure voltage and the amplitude of the erase pulses.

The supplementary porches serving to constitute a write base have anamplitude equal to or greater than the difference between a so-calledwriting voltage and a voltage value formed by the sum of the voltage ofa positive strobe and of the amplitude of a write pulse.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood and other advantages which itaffords will become apparent on reading the description which follows ofcertain of its embodiments, which description is made by way ofnon-limiting example with reference to the appended figures in which:

FIG. 1 already described shows diagrammatically a PAP to which theprocess of the invention may be applied;

FIGS. 2a to 2 f already described represent signals applied according toa known process to electrodes of the PAP of FIG. 1;

FIG. 3 represents an AC PAP implementing the process;

FIGS. 4a to 4 j represent signals applied to the electrodes of the PAPof FIG. 3 in accordance with the process of the invention;

FIG. 5 represents sustain signals in the case of an addressing of theso-called multiple type;

FIGS. 6a, 6 b, 6 c illustrate a version of the invention consisting inmodifying a potential applied to column electrodes;

FIG. 7 illustrates the manner of operation of a control circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 represents a PAP similar to that shown in FIG. 1 except asregards its sustain amplifiers A1′, A2′, which comprise means allowingthe implementation of the process of the invention.

Each amplifier A1′, A2′ comprises a sustain generator 12, 14 which is initself conventional, producing the sustain signals SE, and in contrastto the amplifiers A1, A2 of FIG. 1, they furthermore include a so-called“superposition” circuit 15 cooperating with the sustain generator so asto superimpose voltage signals referred to as “supplementary porches” PSonto the sustain signals SE at given instants. A sustain generator 12,14 can for example comprise a first and a second voltage source 25, 16which are respectively negative and positive, one polarity of which isat the reference potential V0 or earth potential in the example, and theother polarity of which delivers the negative voltage V1 (voltage of thenegative strobes 9) in respect of the source 25, and delivers thepositive voltage V2 (voltage of the positive strobes 10) in respect ofthe source 16. The sustain signal SE delivered at the output 17 of anamplifier A1′, A2′ results from a switching of one of these threepotentials onto this output 17; this switching is accomplished with theaid of three switching elements symbolized in the figure by switches I1,I2, I3 respectively switching the negative potential V1, the positivepotential V2 and the earth potential.

In the non-limiting example described in which the abovementionedsupplementary porches are positive, the superposition circuit 15comprises a third and a fourth voltage source 18, 26 having a polaritylinked to earth; the other polarity of the third and of the fourthsource respectively deliver a positive voltage V7 and a positive voltageV6 which corresponds to the amplitude of at least one of thesupplementary porches. The voltage V7 is equal to the sum of thepositive voltage V2 and of the positive voltage V6 of the supplementaryporches. The voltages V6, V7 may be applied to the output 17 of theamplifier Al′, A2′ with the aid respectively of a fourth and fifthswitching element or switch I4, I5. A diode 19 arranged between theoutput 17 and the fourth voltage source 16 prevents any flow of currentin the latter due to the application of the voltage V7. Of course, asimilar manner of operation carried out in particular with negativevoltage sources 18, 26 would allow the superposition of supplementaryporches of negative polarity.

FIGS. 4a and 4 g to 4 j show signals intended to be applied to lineelectrodes Y1 to Y6 of the PAP represented in FIG. 3, so as to operatethe latter in accordance with the invention. These signals comprisesustain signals SE and erase and write pulses IE, IS, and their shapediffers from that of the prior art signals shown in FIGS. 2a, 2 c, 2 d,2 e in that, according to a characteristic of the invention, theyfurthermore comprise the abovementioned supplementary porches PS1, PS2.

The supplementary porches are superimposed on the sustain signals SE,and the voltage which results from this first superposition forms avoltage base referred to as the addressing base onto which theaddressing pulses IE, IS are themselves superimposed. The sustainsignals SE consist like those shown in FIG. 2a of a succession ofnegative and positive strobes 9, 10, 9′, 10′ separated by intermediateporches 5, 5′; they are established with a period P1 to P4 and withrespect to a reference potential V0 itself applied to the columnelectrodes X1 to X6. The supplementary porches PS1, PS2 encompass theentirety of the pulse or pulses for addressing a selected lineelectrode.

FIG. 4a represents an addressing cycle accomplished with regard to thecells formed by the first line electrode Y1, during a period P1. In thenon-limiting example described, the supplementary porches PS1, PS2 arepositive, they correspond respectively to an erase operation and to awrite operation. The first supplementary porch PS1 is superimposed onthe sustain signals SE over a wide intermediate porch 5. It has avoltage whose absolute value is below that of the voltage V1, V2 of thestrobes. In the example described, the wide intermediate porches 5 beingat the reference potential V0, it is only the voltage V6 of the firstsupplementary porch PS1 which serves as erase base b1 for the erasepulse IE. This voltage V6 has a value of for example 50 volts; byassuming that the erase voltage V4 is of the order of 120 volts, i.e.slightly below those V1, V2 of the negative and positive strobes 9, 10(of the order of 150 volts), when the erase pulse IE is applied andsuperimposed on the said base b1, it is sufficient for its amplitude V3to be of the order of 70 to 80 volts in order for the erase voltage V4to be obtained, and for the erasure to be carried out. The intermediateporch 5 serving to form the erase base b1 is established between anegative strobe 9 followed by a positive strobe 10.

The second porch PS2 is superimposed over the positive strobe 10. Itsvoltage V6 is in the example substantially the same as that of the firstsupplementary porch (it is of course possible if necessary to givedifferent values to the two supplementary porches) and is added to thevoltage V2 of this strobe, to constitute a second voltage base b2intended to receive the write pulse IS. By assuming that the potentialdifference or writing voltage VA necessary for writing the cells is ofthe order of for example 270 volts, and that the voltage of thesupplementary porches PS1, PS2 is of the order of 50 volts, when thewrite pulse IS is superimposed on the said second voltage base b2, it issufficient for it to have an amplitude VS of the order of 70 volts inorder for the write voltage VA, that is to say the turn-on voltage, tobe obtained.

As far as the first porch PS1 is concerned, it is applied broadly afterthe instant td1 of the sustain discharge due to the establishment of anegative porch p−, and it is completed before the start of the positiveporch p+ which follows and hence before the instant td2 of the dischargewhich follows. Of course, its amplitude V6 should remain sufficientlybelow the voltage of the sustain signals SE so as not itself to giverise to any discharge (having regard in particular to the scatter in thecharacteristics exhibited by the cells).

The second porch PS2 is superimposed on the positive strobe 10, afterthe instant td2 at which a sustain discharge occurs, and its presencetherefore in no way affects the conditions of this discharge. Itsamplitude should of course remain limited to a value such that, whenadded to the voltage V2 of the strobe 10, the resulting voltage remainsbelow that which is able to cause discharges of the write dischargestype. In the non-limiting example represented, the second supplementaryporch PS2 terminates in phase with the end of the strobe 10:consequently, the voltage transition which follows and which leads tothe reference potential V0 has a larger amplitude than that which itwould have in the absence of the second supplementary porch PS2, butwhich has only a slight influence on the sustain discharge arising atthe instant td4 which follows, since this discharge is caused by thepotential difference engendered with the establishment of the negativestrobe 9 belonging to the following period P2. It may be seen that,under these conditions, the superimposition onto the sustain signals SEof the first or of the second supplementary porch PS1, PS2 or of boththese porches PS1, PS2 cannot significantly affect the sustaindischarges.

Rather than being positive, the supplementary porches PS1, PS2 and thewrite pulse IS and erase pulse IE may be negative as illustrateddiagrammatically in FIG. 4j in respect of the addressing of the lineelectrode Y1. The first negative supplementary porch PS1 could be addedto a wide intermediate porch 5′ leading to a negative strobe 9′ of thesustain signal SE. A negative erase pulse IE would be added to the Firstsupplementary porch PS1. The intermediate porch 5′ serving to form anerase base would be established between a positive strobe 10′, followedby a negative strobe 9′ of the sustain signal SE. The second negativesupplementary porch PS2 would be superimposed on a negative strobe 9′ ofthe sustain signal SE. It would constitute a voltage base b2 to whichthe likewise negative write pulse IS would be added.

FIGS. 4b, 4 c, 4 d, 4 e, 4 f to be read in conjunction with FIG. 4a showrespectively the action of the first, second, third, fourth, and fifthswitches I1, I2, I3, I4 and I5 and illustrate the operation of a signalgenerator 12 cooperating with its superposition circuit 15, so as toproduce, during the first period P1, the sustain signals SE togetherwith superimposed supplementary porches.

With the start of the period P1, the first switch I1 is “closed” (theother switches are “open”) and applies the negative voltage V1 whichcorresponds to the negative porch p−. At the end of the porch p−, thefirst switch I1 passes to the “open” state and the fourth switch I4passes to the “closed” state, this determining the wide intermediateporch 5, together with the first superimposed supplementary porch PS1.At the end of the wide porch 5, the switch I4 passes to the “open” stateand the second switch I2 is closed and applies the voltage V2corresponding to the positive porch p+of the positive strobe 10. Thesecond switch I2 retains its “closed” state until after the instant td2at which a sustain discharge occurs, then it is open and it is the fifthswitch I5 which passes to the closed state and applies the voltage V7corresponding to the second supplementary porch PS2. At the end of thepositive strobe 10, the fifth switch I5 is open and the third switch I3passes to the closed state and applies the potential of earth; thiscorresponds to establishing the narrow intermediate porch 11 until thestart of the negative strobe 9 which follows and which belongs to afollowing period P2.

The supplementary porches PS1, PS2 may be formulated and superimposed onthe sustain signals in various ways. For example, this can be achievedin a simple manner in each of the sustain generators 12, 14 in such away that these supplementary porches PS1, PS2 are applied simultaneouslyand continuously to all the line electrodes Y1 to Y6 of the PAP, oralternatively in such a way that these supplementary porches are appliedsolely to those of the line electrodes which are linked to a linecontrol circuit 6, 7 currently carrying out an addressing. This lattermethod corresponds to the example represented with the aid of FIGS. 4aand 4 g to 4 i, which illustrate the fact that, on the one hand, thesustain signals SE distributed to the line electrodes Y1, Y2, Y3 (alllinked to the first line control circuit 6) possess supplementaryporches PS1, PS2, and on the other hand that the sustain signals SEapplied to the line electrodes Y4, Y5, Y6 (all linked to the second linecontrol circuit 7, and none of which is undergoing addressing) do notpossess these porches until the arrival of the day of the month periodP4.

The addressings (illustrated in FIGS. 4h, 4 g) on the line electrodesY2, Y3 are performed during the periods P2, P3 respectively, with theaid of the supplementary porches and of the erase and write pulses IE,IS as explained above.

FIG. 4i represents the addressing performed at the period P4 whichfollows, on the fourth line electrode Y4 which it depends of the secondline control circuit 7. In the non-limiting example represented, theperiod P4 is that onwards of which the superposition of thesupplementary porches PS1, PS2 onto the sustain signals SE distributedto the electrodes Y1 to Y3 ceases, and where conversely thissuperposition starts on the signals SE distributed to the electrodes Y4to Y6. The addressing on the line electrode Y4 as well as thoseaddressings (not represented) performed subsequently at periods whichfollow on the electrodes Y5, Y6 are performed in the same manner asexplained above, by superimposing supplementary porches and erase andwrite pulses IE, IS.

Such a manner of operation therefore makes it possible, as compared withthe prior art: to use line control circuits of lower performance, on theone hand owing to the reduction in the amplitudes of the addressingpulses IS, IE, and on the other hand owing to the fact that thesupplementary porches PS1, PS2 which compensate for this amplitudereduction pass through the line control circuits 6, 7 through the samepathway as the sustain signals SE.

This manner of operation furthermore makes it possible, through thesuperimposing of the erase and write pulses IE, IS onto alreadyestablished supplementary porches PS1, PS2, as well as through thereduction in the amplitude of these pulses, to reduce the capacitiveconsumption due to the application of these pulses. This reduction incapacitive consumption is especially manifest when the addressingfrequency is very high, in particular in the addressings of theso-called “multiple pulse” type, in which may be found a large number ofselective-addressing pulses (usually in write mode) on one and the samestrobe. Accordingly, the process of the invention makes it possible toreduce the amplitude of a large number of these pulses by superimposinga single supplementary porch.

FIG. 5 represents the shape of the sustain signals SE′ for such a caseof “multiple pulse” addressing. In the example of FIG. 5, a period P′ 1of the signals SE′ making it possible to perform an addressing cyclestarts with a negative strobe 9, followed by a positive strobe 10 a fromwhich it is separated by a wide intermediate porch 5 formed at the levelof the reference potential V0; this positive strobe 10 a is followed bya narrow intermediate porch 11 preceding another negative strobe 9 whichis itself followed by a narrow porch 11; next comes a narrow positivestrobe 10 b, and then finally a narrow intermediate porch 11 whichprecedes a negative strobe of a following period P2′. It should be notedthat the sole function of the last negative and positive strobes 9, 10 bbeing to cause sustained discharges, no supplementary porch issuperimposed on them.

In the example represented, the negative strobe 9 has a duration T1which is much less than the duration T2 of the positive strobe 10 a,which duration T2 corresponds to the time required to carry out theselective addressing of the cells formed along several line electrodesgenerally controlled by the same line control circuit, as is the casefor example for the groups of line electrodes Y1 to Y3 and Y4 to Y6,these groups being controlled by the control circuits 6, 7 respectively.

It should be noted that control circuits of the type of the circuits 6,7 are commonly found which have several outputs each linked to a lineelectrode.

Each of these control circuits can have for example 32, 40, 64 or even128 outputs.

As many outputs must be provided as the number n of line electrodes.These control circuits make it possible:

on the one hand, to apply, to one or simultaneously to several selectedelectrodes or to n electrodes, for example an erase pulse IE which mayin the prior art be superimposed directly on a wide intermediate porch5, so as to simultaneously erase all the cells of all the electrodes towhich it is applied;

on the other hand, receiving a string of write pulses IS1, IS2, IS3, . .., ISn, these control circuits employ means which allow them todistribute each write pulse to a line electrode, one electrode afteranother; these write pulses are each superimposed on the same positivestrobe of the signals SE, at different instants along this strobe. Thewriting of the cells of the n line electrodes may thus be accomplishedwith the aid of a single strobe 10 a, at high speed.

This organization according to the prior art is illustrated FIG. 5 inwhich, in addition, and according to the invention, there is at leastone supplementary porch serving for the erase pulse IE and/or for thewrite pulses IS1 to ISn. In the example represented, a firstsupplementary porch PS1′, having for example the same shape and the samevalue as those of the first porch PS1 shown in FIG. 4a (assuming thatthe strobes of the sustain signals SE of FIG. 4a have the same value V1,V2 as those of the signals SE′ of FIG. 5) is superimposed on the wideintermediate porch 5 contained in the period P′ 1. Hence, an erase pulseIE (symbolized in FIG. 5 by dashed lines) having the same value as thatof FIG. 4a can be superimposed on the base b1′ consisting of thissupplementary porch, so as to carry out the erasure.

A second supplementary porch PS2′ is superimposed on the first positivestrobe 10 a, after the instant td at which the sustain dischargeproduced by the establishment of this strobe occurs. This secondsupplementary porch PS2′ lasts till the end of the positive strobe 10 a,and its voltage value may be the same as that of the secondsupplementary porch PS2 shown in FIG. 4a. Writes may therefore beobtained by superimposing write pulses IS1, IS2, . . ., ISn, on thevoltage base b2′ resulting from the voltages of this supplementary porchPS2′ and the positive strobe 10 a, and by distributing these signals tothe line electrodes as explained above.

It is also conceivable, in the case of “multiple pulse” addressing, forthe supplementary porches PS1, PS2 to be negative and for them to beadded respectively to an intermediate porch and to a negative strobe ofthe sustain signal. A negative erase pulse would be added to the firstsupplementary porch PS1 and several write pulses would be added to thesecond supplementary porch PS2.

FIGS. 6a, 6 b, 6 c represent another way of compensating for thereduction in the amplitude of the write and erase pulses, this wayconsisting in modifying the voltage applied to the column electrodes X1to X6, or at least to those of these electrodes which define anaddressed cell.

FIG. 6a represents a period P′ 1 of sustain signals SE′ similar to thoseof FIG. 5 (that is to say allowing addressing of the “multipleaddressing” type), which period illustrates an addressing sequenceperformed according to this new version of the process of the invention.These signals comprise a negative strobe 9 and a positive strobe 10 awhich are separated by a wide intermediate porch 5. This porch 5 andthis strobe 10 a are intended to receive, respectively, an erase pulseIE and write pulses IS1, IS2, with no prior superposition ofsupplementary porches.

FIG. 6b represents variation of a voltage VX applied to a columnelectrode, the second electrode X2 for example (this example holding forall the other column electrodes X1 to X6); these variations are due tosignals consisting on the one hand of masking pulses IM (which opposethe execution of an addressing), and on the other hand of so-called“confirmation” pulses or strobes 30, 31 which on the contrary favour theexecution of the addressing. In the absence of these pulses, the voltageVX applied by the output SX2 to the electrode X2 has a value VX0corresponding to the reference potential V0.

When the erase pulse IE is superimposed on the wide porch 5, theresulting voltage reaches a value V3 (of 80 volts for example) which isbelow that of the voltage V4 (of the order of 120 volts) required toaccomplish erasure. The difference V4−V3 is then compensated for by thevoltage VX applied to the electrode X2: with this objective, a negativestrobe forming an erase confirmation pulse 30 having an amplitude Vce(of the order of 40 volts for example) is then applied (in phase withthe erase pulse IE), causing the voltage VX to pass to a value −VX. Theeffect of this is to increase the potential difference applied to theterminals of the cells to be “erased” until it is made to reach thevalue of the erase voltage V4. The column voltage VX then re-attains thevalue of the reference potential V0 until the write phase, or at leastuntil after the instant td at which a sustain discharge occurs.

The confirmation pulses have an amplitude equal to or greater than adifference between the addressing voltage and the voltage which on theselected line electrode results from the addressing pulse.

By assuming on the one hand that this write phase comprises a first anda second write pulse IS1, IS2 which are consecutive (applied todifferent line electrodes), having an amplitude V5 such that when thesepulses are superimposed on the positive strobe 10 a, the resultingvoltage V2+V5 is below the value VA required for writing; by assuming onthe other hand that a cell defined by the second column electrode X2 hasto be set to the written state by the first pulse IS1, a negative strobe31 constituting a write confirmation pulse having an amplitude Vci (ofthe order of 40 volts for example) is then applied to the secondelectrode X2 (in phase with the first write pulse IS1). Consequently,the voltage VX on this column passes to the negative value −VX, and thisvariation in the voltage VX increases the potential difference appliedto the cell until it is made to reach the value VA required for writes.

Assuming lastly that another cell defined by the second column electrodeX2 has to retain an “erased” state despite the application of the secondwrite pulse IS2: it is sufficient to apply to the column electrode X2(in phase with the second write pulse) a strobe which is positive withrespect to the potential V0 (of the order of 40 volts), so as to makethe voltage VX on the column electrode pass to a positive value +VX andconstitute a masking pulse IM1.

The manner of operation described with reference to FIG. 6b requiresthat means of switching and/or of pulse superposition of the columncontrol circuit 8 be organized so as to allow it to deliver as outputSX1 to SX6, pulses which are positive and negative with respect to amid-point (earth for example).

FIG. 7 diagrammatically represents such an organization, in which theclosing of a first or of a second or of a third switch element I′1, I′2,I′3 causes respectively the application to a column electrode X1 to X6,of the earth, of the negative voltage −VX, of the positive voltage +VX.In the non-limiting example described, the earth here constitutes thereference potential with respect to which the voltages of the sustainsignals are alternately positive and negative, but also constitutes thereference voltage V0′1 specific to the operation of the elements of thecolumn control circuit 8, and with respect to which voltage the pulses30, 31 and IM1 are delivered.

FIG. 6c illustrates another method for carrying out the same addressingsequence as that of FIG. 6b with addressing pulses IE, IS1, IS2 ofreduced amplitude, which makes it possible to use the outputs of thecolumn control circuit 8 in a manner which is more in keeping with itsmost common capabilities, and in which the reference voltage V0′1specific to the control circuit 8 is always negative with respect to thepulses 30, 31, IM1 delivered.

Before the start of the wide intermediate porch 5 to which the erasepulse IE is applied (FIG. 6a), the voltage VX on the column electrode X2possesses the value VX0 corresponding to the reference potential V0, butwhich also corresponds to the first reference voltage V0′1 specific tothe operation of the column control circuit 8. When the wideintermediate porch 5 occurs, the confirmation strobe or pulse 30 whichis constructed on the voltage VX results from a change of referencevoltage specific to the control circuit: indeed, via switching (notrepresented, within the scope of any expert in the field), the firstreference voltage V0′1 specific to the circuit 8 is replaced with asecond reference voltage V0′2 which is negative with respect to thefirst and which corresponds to the value of the negative voltage −VX.This second reference voltage V0′2 is retained up to the start of thepositive strobe 10 a which follows, onwards of which it is substitutedby the first reference voltage V0′1, so as to bring about the end of theerase confirmation pulse 30 before the instant td of a sustain dischargeand not to risk modifying the conditions of the latter. The eraseconfirmation is thus as it were built into the reference voltage.

After this instant td of a discharge, and in phase or before theapplication of the first write pulse IS1, the second reference voltageV0′2 again replaces the first so as to produce the write confirmationpulse 31. The first reference voltage V0′1 is then substituted for thesecond reference voltage V0′2 so as to form the end of this writeconfirmation. Next, before or in phase with the second write pulse IS2,a positive pulse is applied with respect to the value VX0 whichrepresents the reference potential V0 as well as the first referencevoltage specific to the circuit 8, which positive dulse constitutes amasking pulse IM1 and which, over its duration, confers the value +VX onthe voltage VX.

It should be observed that the compensations for potential differenceseffected at the level of the voltage applied to the column electrodes X1to X6, as described above, are especially advantageous as regards thereducing of the capacitive power (owing in particular to the fact thatthey lead to a large reduction in the amplitude of the masking pulses)since the capacitance seen by the pulses distributed over the columns X1to X6 is much larger than that encountered on the line electrodes Y1 toY6.

Of course, the reduction in the amplitude of the addressing pulses IE,IS may also be compensated for by combining the amplitude of thesupplementary porches with the amplitude of the confirmation strobes.

This description of the process of the invention and of the means whichare useful for its implementation has been made with reference to an ACPAP using only two crossed electrodes to define a cell, but theinvention nevertheless applies to all types of AC PAPs, including thoseof the so-called “coplanar sustain” type. In this latter type of PAP infact, the problems related to the amplitude of the addressing pulses arethe same, and the solutions described above apply in the same way sincethe addressing is performed with the aid of two crossed electrodes, oneof which receives sustain signals, as described herein.

What is claimed is:
 1. Control process for addressing an AC plasma panelcomprising at least one network of line electrodes, crossed with atleast one network of column electrodes, cells being formed at theintersections of the line and column electrodes, said processcomprising: applying to all the line electrodes, sustain signals made ofa succession of strobes established with a given period with respect toa reference potential applied to the column electrodes, each periodcomprising an addressing cycle comprising at least one semi-selectiveaddressing and at least one selective addressing, each type ofaddressing comprising applying to at least one selected line electrodean addressing pulse whose voltage is added to a line voltage alreadypresent on this electrode, with a view to applying to the terminals ofcells formed by this selected electrode an addressing voltage of givenvalue corresponding to the addressing to be performed, wherein for atleast one of the semi-selective addressing and the selective addressing,the addressing pulse has an amplitude below that which is appropriatefor obtaining the required addressing voltage, and in that to obtain therequired addressing voltage, the process comprises one of: (1) modifyingthe reference potential applied to the column electrodes, (2) modifyingthe line voltage already present on the selected line electrode when theaddressing pulse is applied, and (3) in modifying the line voltage aswell as the reference potential applied to the column electrodes. 2.Process according to claim 1, wherein the semi-selective and selectiveaddressings respectively comprise erasures and writings of cells. 3.Process according to claim 1, comprising superimposing at least onevoltage porch referred to as the supplementary porch on the sustainsignals to form a voltage base referred to as the addressing base ontowhich is superimposed at least one addressing pulse.
 4. Processaccording to claim 3, wherein the supplementary porches are positive ornegative voltage porches added to the sustain signals.
 5. Processaccording to claim 1, the sustain signals being formed of negative andpositive strobes, the process comprising forming a write addressingvoltage base with a strobe, and of superimposing an addressing pulsecomprising a write pulse onto the write addressing voltage base. 6.Process according to claim 3, comprising establishing between twoconsecutive strobes an intermediate porch having a voltage below thevoltage of the strobes, and in adding a supplementary porch to the saidintermediate porch to form an erase addressing base, then insuperimposing an addressing pulse comprising an erase pulse onto theerase addressing base.
 7. Process according to claim 6, wherein theintermediate porch serving to form an erasure base is establishedbetween a negative strobe followed by a positive strobe.
 8. Processaccording to claim 6, wherein the intermediate porch serving to form anerasure base is established between a positive strobe followed by anegative strobe.
 9. Process according to claim 1, wherein thesupplementary porches are added onto strobes, being superimposed on thestrobes after an instant at which a sustain discharge occurs. 10.Process according to claim 9, wherein the supplementary porches formedon the strobes are deleted substantially at the end of the strobes. 11.Process according to claim 3, comprising superimposing severaladdressing pulses onto the same addressing base.
 12. Process accordingto claim 1, wherein the supplementary porches formed on the strobesencompass an entirety of the pulse or pulses for addressing the selectedline electrode.
 13. Process according to claim 6, wherein the eraseaddressing base has an amplitude equal to or greater than the differencebetween an erasure voltage and the amplitude of the erase pulses. 14.Process according to claim 5, wherein the write addressing voltage basehas an amplitude equal to or greater than the difference between awriting voltage and a voltage value formed by the sum of the voltage ofa positive strobe and of the amplitude of a write pulse.
 15. Processaccording to claim 6, wherein the intermediate porch is at a samevoltage as the reference potential.
 16. Process according to claim 1,wherein the sustain signals are formulated by at least one sustainamplifier and then applied to a line control circuit so as to bedistributed to the line electrodes, and wherein the supplementaryporches are superimposed on the sustain signals before being applied tothe line control circuit.
 17. Process according to claim 16, comprisingdistributing the sustain signals to the line electrodes via at least twoline control circuits, and applying sustain signals together withsuperimposed supplementary porches only to that of the control circuitswhich controls a line electrode for which an addressing is in progress.18. Process according to claim 1, wherein for at least one of theaddressings the process comprises modifying the reference potentialapplied to the column electrodes in synchronism with the addressingpulses, by superimposing confirmation pulses, having a polarity oppositeto those of the addressing pulses, onto the said reference potential.19. Process according to claim 18, wherein, for the selectiveaddressing, the process comprises superimposing either a confirmationpulse or a masking pulse of polarity opposite to that of theconfirmation pulse onto the said reference potential.
 20. Processaccording to claim 18, wherein the confirmation pulses have an amplitudeequal to or greater than a difference between the addressing voltage andthe voltage which on the selected line electrode resulting from anapplication of the addressing pulse.
 21. Process according to claim 18,wherein the reference potential applied to each column electrode isdelivered by a column control circuit having n outputs, each outputbeing capable of delivering negative pulses and positive pulses withrespect to the reference potential.
 22. Process according to claim 18,wherein the reference potential applied to each column electrode isdelivered by a column, control circuit having n outputs, each outputbeing capable of delivering negative pulses and positive pulses withrespect to the reference potential, and in that one or other of thesetwo pulse types results from a modification of a reference voltagespecific to an operation of the column control circuit.
 23. Plasma panelof AC type implementing the process according to claim 1, comprising atleast one network of line electrodes crossed with at least one networkof column electrodes, a column management device linked to the columnelectrodes, a line management device comprising at least one sustainamplifier delivering sustain signals applied to the line electrodes byway of a line control circuit, cells being formed at the intersectionsof the line and column electrodes, semi-selective addressing pulses andselective addressing pulses being superimposed on the sustain signals soas to apply to the terminals of selected cells an addressing voltagehaving a given value depending on the addressing to be performed,wherein for at least one of the semi-selective and selective addressing,the line management device or the column management device or the twodevices comprise means for creating a voltage which is added to avoltage resulting from superimposing the addressing pulse onto thesustain signals.
 24. Plasma panel according to claim 23, wherein theline management device comprises a superimposing circuit configured tosuperimpose supplementary porches onto the sustain signals.
 25. Plasmapanel according to claim 24, wherein the sustain amplifier cooperateswith the superimposing circuit to superimpose the supplementary porchesonto the sustain signals before applying the supplementary porches tothe line control circuit.